FIGS. 11 and 12 are diagrams schematically showing configuration of a known SRAM.
As shown in FIG. 11, a known SRAM (Static Random Access Memory) 101 has a final decoder 102, a control generator 103, a clock generator 104, read/write blocks 106a and 106b, I/O circuits 105a and 105b, and memory cell arrays 107a and 107b. 
Each of the memory cell arrays 107a and 107b has a plurality of memory circuits called memory cells which hold data, and is connected to a bit line.
The read/write blocks 106a and 106b each writes and reads data to and from the memory cell array 107a and 107b via the bit line, having a sense amplifier (not shown), etc., for example. Incidentally, the read/write block 106a performs the processes on the memory array 107a, while the read/write block 106b performs the processes on the memory array 107b. 
The I/O circuits 105a and 105b exchange data between the SRAM 101 and the outside. The I/O circuit 105a is provided for the read/write block 106a, while the I/O circuit 105b is provided for the read/write block 106b. 
The final decoder 102 performs address decoding of the memory cells. The clock generator 104 generates a clock for operations of the SRAM 101, and performs the pre-decoding process. The control generator 103 performs various controls via the read/write blocks 106a and 106b. 
In the SRAM 101 shown in FIG. 11, the sense amplifier in each of the read/write blocks 106a and 106b detects a minute difference in amplitude in the memory cell in the read operation, and amplifies the difference to read the data.
In these years, the SRAM 101 is configured more minutely, which degrades the conditions for data reading in the SRAM 101. In order to overcome the degradation of the reading conditions in the SRAM 101 configured minutely, there has been proposed a technique that divides the bit line into a plurality of portions (blocks) to decrease the load at the time of the data reading (refer to Patent Document 1, etc. below).
In the SRAM 101 shown in FIG. 12, each of the bit lines in the SRAM 101 shown in FIG. 11 is divided into four blocks (local blocks) to divide the memory cell array 107a into four local blocks 110a-0 to 110a-3. Similarly, the memory cell array 107b is divided into four to form local blocks 110b-0 to 110b-3.
In the example shown in FIG. 12, the read/write block 106 is formed in each of the local blocks 110a-0 to 110a-3 and 110b-0 to 110b-3, and two memory cell arrays 107 and 107 are formed, sandwiching the read/write block 106. The read/write block 106 controls these two memory cell arrays 107 and 107.
For example, between the local blocks 110a-3 and 110b-3, formed is a control block CB03, in which a control generator 103 is formed, together with two final decoders 102 and 102 sandwiching the control generator 103. The two final decoders 102 and 102 are formed, correspondingly to two memory cell arrays 107 and 107 in the adjacent local blocks 110.
In the example shown in FIG. 12, the read/write block 106 and the two memory cell arrays 107 are shown in only the local block 110b-3, for the sake of convenience. Like the local block 110b-3, the read/write block 106 and the two memory cell arrays 107 are provided in each of the other local blocks 110a-0 to 110a-3, and 110b-0 to 110b-2.
Similarly, in the example shown in FIG. 12, the control generator 103 and the two final decoders 102 are shown in only the control block CB03, for the sake of convenience. Like the control block CB03, the control generator 103 and the two final decoders 102 are provided in each of the other control blocks CB00 to CB02.
Incidentally, like reference characters in the drawings designate like or corresponding parts, detailed description of which are omitted here.
As shown in FIG. 12, the memory cell arrays 107a and 107b are divided into a plurality of blocks to form a plurality of local blocks, which makes it possible to read data from each memory cell at high speed. At the same time, discharging of the bit lines can be done at high speed, which can shorten the unstable period of the memory cell.
[Patent Document 1] Japanese Patent Application Laid-Open Publication No. HEI11-110969
However, in such the known SRAM 101 shown in FIG. 12, the read/write block is required in each of the local blocks 110a-0 to 110a-3 and 110b-0 to 110b-3, which increases the macro area according to the number (dividing number) of the formed local blocks 110a-0 to 110a-3 and 110b-0 to 110b-3.
In the designing stage, it is required to design the read/write block 106 with the minimum configuration in order to suppress an increase in area of the read/write blocks 106. However, simplification of the configuration of the read/write block 106 makes it difficult to gain attentive controls at the time of reading and writing, separately, resulting in that the write data drives circuits and a read output terminal that do not relate to the operation through the bit line, which increases the power consumption.
FIG. 13 is a diagram showing an example of circuit configuration of part of a known SRAM 101.
The known SRAM 101 shown in FIG. 13 has a memory cell 1071, a write driver 1061, a GBL reset 1062, a write amplifier 1063, a GBL driver 1064, a column switch 1065, a sense amplifier 1066 and a pre-charge/equalizer 1067.
Among them, the GBL driver 1064, the column switch 1065, the sense amplifier 1066 and the pre-charge/equalizer 1067 are formed in the read/write block 106, for example.
In FIGS. 13, a reference character WL a word line, SAEN a sense amplifier enable signal, PC_B a bit line pre-charge signal and CSEL a column selection signal.
Reference characters DIT and DIC designate write signals. The write signal DIT designates a true signal, while the write signal DIC designates a complementary signal thereof. Similarly, reference characters BL and BLB designate local bit lines. The local bit line BL is a true value, while the local bit line BLB is a complementary signal thereof.
A reference character GBL designates a global bit line, WCK a pulsed clock signal, and WE a write enable signal. A reference character DI designates an input signal, which is data inputted from the outside of the SRAM 101.
The GBL driver 1064 sends out a read signal, which has been read out from the memory cell 1071 and amplified by the sense amplifier 1064, to the global bit line GBL, and sends out a write signal, which has been inputted from the write driver 1061 and amplified by the write amplifier 1063, to the local bit lines BL and BLB.
In the known SRAM 101 shown in FIG. 13, the GBL driver 1064 has PFETs 651 and 652, and NFETs 653 to 655.
The PFET 651 has a gate terminal to which the local bit line BL is connected, a source terminal to which a power source is connected, and a drain terminal to which a source terminal of the PFET 652 is connected.
The FET 652 has a gate terminal to which the column selection signal CSEL can be inputted, and a drain terminal to which a drain terminal of the NFET 653, a drain terminal of the NFET 654 and a gate terminal of the NFET 655 are connected.
The NFET 653 has a gate terminal to which the pre-discharge signal PDC can be inputted, and a source terminal which is grounded.
The FET 654 has a gate terminal to which the global bit line GBL is connected, and a source terminal which is grounded. The NFET 655 has a drain terminal to which the global bit line GBL is connected, and a gate terminal to which the drain terminal of the PFET 652 is connected. A source terminal of the NFET 655 is grounded.
FIG. 14 is a timing chart showing an example of state of signals at the time of data writing in the known SRAM. In FIG. 14, a reference character CLK designates a system clock.
Assuming here that the memory cell 1071 is selected at the time of data writing in the known SRAM 101, that is, “0” is set as the column selection signal CSEL (refer to a point C1 in FIG. 14), and “0” is inputted as both the write enable signal WE and the input signal DI to the write driver 1061 (refer to “cycle 2” in FIG. 14) (refer to point C2 in FIG. 14).
Since “0” is inputted as both the write enable signal WE and the input signal D1, the local bit lines BL is discharged. On this occasion, the PFET 652 is turned on, hence the local bit line BL and the global bit line GBL are connected.
Namely, in the GBL driver 1064, the global bit line GBL is discharged via the PFETs 651 and 652 (refer to point C3 in FIG. 14), whereby “0” is outputted as the read signal RD in cycle 3 (refer to point C4 in FIG. 14).
In the known SRAM 101, in “cycle 1” where the write enable signal WE is “0” and the input signal DI is “1” , the global bit line GBL keeps “1”, hence “1 (High)” is kept as the read signal RD. In “cycle 2” where the write enable signal WE is “0” and the input signal DI is “0”, the GBL driver 1064 is operated to discharge the global bit line GBL, hence “0” is outputted as the read signal RD in cycle 3.
In other words, the write signal DIT is outputted to the global bit line GBL via the PFETs 651 and 652 for reading use.
As above, since the write signal DIT is outputted to the global bit line GBL at the time of data writing, other circuits (not shown) and the read output terminal (not shown) which do not relate to the operation are driven, which increases the power consumption of the SRAM.